One of the most annoying things when working on an early design on an FPGA development kit is a lack of run-time register interfaces without a lot of effort.
While looking for an interface that would work on basically any Vivado supported Xilinx FPGA I came across the JTAG to AXI Master core supplied by Xilinx. Unfortunately it has a cumbersome interface that is intended for the user to drive from Vivado’s TCL console which is not always the most convenient. Others have been looking for a C API to interact with the hw_server directly. There seems to be someone that has had put together a C library but I was unable to get the files. I wanted something easier to use anyways so I began to look elsewhere for a solution.Continue reading FPGA – Xilinx JTAG to AXI Master from XSDB and Python