Monthly Archives: December 2022

FPGA

FPGA – Xilinx JTAG to AXI Master from XSDB and Python

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One of the most annoying things when working on an early design on an FPGA development kit is a lack of run-time register interfaces without a lot of effort.

While looking for an interface that would work on basically any Vivado supported Xilinx FPGA I came across the JTAG to AXI Master core supplied by Xilinx. Unfortunately it has a cumbersome interface that is intended for the user to drive from Vivado’s TCL console which is not always the most convenient. Others have been looking for a C API to interact with the hw_server directly. There seems to be someone that has had put together a C library but I was unable to get the files. I wanted something easier to use anyways so I began to look elsewhere for a solution.

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FPGA

FPGA – LittleRiscy RISC-V RV32I Emulator and HDL Core

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LittleRiscy is an RV32I RISC-V emulator and HDL core that I have decided to release as an open source project. The project is a work in progress.

LittleRiscy’s GIT repository contains an instruction set emulator written in C++ and a CPU core written in SystemVerilog. The emulator has been validated against some simple test binaries and the SystemVerilog code has been converted to C++ using Verilator to validate that it behaves functionally identical when running the same test binaries.

At this time, LittleRiscy has been deployed on a Xilinx Series 7 FPGA using Xilinx Vivado and has blinked some LEDs with a simple binary.

The goal of LittleRiscy is to create a simple CPU core for a unique purpose. It will be a classic RISC pipeline with no debugger, no interrupts, no ability to load new code at runtime, and limited peripherals. Inspired by CHIPS2.0 and the PIOs in the RP2040, it will be used to process AXI-Streams for packet processing or digital signal processing when data rates are low enough that custom RTL logic is not required and a CPU is both smaller and simpler. To further simplify creation of software for the core, the AXI-Stream input interface could stall the CPU on read if empty and the output interface could stall the CPU on write if full, negating the requirement for the software to check flags during execution. For some demanding tasks, it should be easy to add a handful of custom instructions to improve throughput.