One of the most annoying things when working on an early design on an FPGA development kit is a lack of run-time register interfaces without a lot of effort.
While looking for an interface that would work on basically any Vivado supported Xilinx FPGA I came across the JTAG to AXI Master core supplied by Xilinx. Unfortunately it has a cumbersome interface that is intended for the user to drive from Vivado’s TCL console which is not always the most convenient. Others have been looking for a C API to interact with the hw_server directly. There seems to be someone that has had put together a C library but I was unable to get the files. I wanted something easier to use anyways so I began to look elsewhere for a solution.
LittleRiscy is an RV32I RISC-V emulator and HDL core that I have decided to release as an open source project. The project is a work in progress.
LittleRiscy’s GIT repository contains an instruction set emulator written in C++ and a CPU core written in SystemVerilog. The emulator has been validated against some simple test binaries and the SystemVerilog code has been converted to C++ using Verilator to validate that it behaves functionally identical when running the same test binaries.
At this time, LittleRiscy has been deployed on a Xilinx Series 7 FPGA using Xilinx Vivado and has blinked some LEDs with a simple binary.
The goal of LittleRiscy is to create a simple CPU core for a unique purpose. It will be a classic RISC pipeline with no debugger, no interrupts, no ability to load new code at runtime, and limited peripherals. Inspired by CHIPS2.0 and the PIOs in the RP2040, it will be used to process AXI-Streams for packet processing or digital signal processing when data rates are low enough that custom RTL logic is not required and a CPU is both smaller and simpler. To further simplify creation of software for the core, the AXI-Stream input interface could stall the CPU on read if empty and the output interface could stall the CPU on write if full, negating the requirement for the software to check flags during execution. For some demanding tasks, it should be easy to add a handful of custom instructions to improve throughput.
Recently I started using an FTDI FT232H in FT245 synchronous FIFO mode with an Intel MAX10 FPGA. I am using an FT232R based USB Blaster (Not a USB Blaster II, this is an older Altera USB Blaster, Terasic USB Blaster or another clone). Unfortunately when Quartus looks for programming devices it fails if it sees the FT232H first and the FT232H is in use by another program.
During the academic year of 2016-2017 at McMaster University, in conjunction with Dr. DeBruin, Christina Riczu, Thomas Phan and Emilie Corcoran, we developed a compact, battery powered, 12-lead electro-cardiogram. The project won 1st place in the biomedical category at the ECE Capstone Poster Day.
The final report we handed in for the course is attached at the end of this post and includes background information, a design overview, schematics and bill of materials for the hardware we developed. This post will introduce the project and serve as a personal account of the considerations and problems associated with the portion of the project that I focused on.
As a gift to my sister and her husband for their wedding I developed the electronics and firmware for a table centerpiece. The product was developed using tools and materials already familiar to me to tighten the development cycle so some component choices were not ideal but were chosen because I already had programmers on hand, code already written, or schematic and footprint libraries already created for past projects. This significantly de-risked manufacturing as many components of the product were already verified to be working giving me confidence to order boards and parts for twenty of these lamps all at once. Developed in about two weeks and all twenty assembled in a weekend this project was completed quickly as the big day was rapidly approaching when I returned to Canada after my internship in California summer of 2016.
Previously, I wrote about the Cypress PSoC5LP microcontroller that I have been playing with. The CY8C5888LTI-LP097 on the CY8CKIT-059 dev-kit can be used to make a very crude radio transmitter. Today I will be explaining how to make some simple transmissions from a PSoC to a computer equipped with an RTL-SDR and SDR# acting as our radio receiver. We will be using configurable digital hardware to create the transmitter.
NOTE: If you decide to recreate my experiment, you should take a look at your country’s regulations for radio communicating devices. For example, the FCC in the United States allows hobbyists to create and operate up to 5 low power devices without a license as long as you follow some rules. Still, be responsible and don’t operate this for any longer then you need to know it works.
I recently picked up a Cypress CY8CKIT-059 to play with for about $10 from Mouser. The kit contains a CY8C5888LTI-LP097 chip that features an ARM Cortex M3 that can run up to 80 Mhz, pretty run of the mill. However, the chip also features a small amount of CPLD resources and configurable datapaths that can be used to implement any digital logic that you can fit in. Cypress calls these blocks universal digital blocks. You can implement your own logic blocks in Verilog or use Cypress’s IP cores that are included with PSoC Creator. The idea is to avoid predefining how many UART, I2C, SPI or other interfaces to include which gives you more freedom to choose the combinations of peripherals you need rather than using pin muxes like on Microchip PIC’s and Atmel AVR’s for example. With the PSoC 5LP you can have 5 UARTs if you wanted and you can put those UARTs on any GPIO pin you want.
Listening to stereo music through headphones has never sounded quite right to me. The extreme stereo separation can cause headaches for me when using headphones for more than an hour. Some people report experiencing “pressure” in their ears when using headphones This discomfort could simply be due to how unnatural headphone listening is; no sound from the left channel makes it to your right ear and vice versa. There are some tricks that can be used to get rid of these problems but before I show you how you can try out these tricks let’s get into the math and science behind head related transfer function (HRTF) and how they are used to simulate the way sound travels to our ears resulting in a better listening experience when using headphones with stereo content or even create what is known as virtual surround sound. Continue reading Head Related Transfer Functions and Headphone Listening→