March 19, 2023 – Initial
I get asked pretty often about how to get into FPGA design or how to become a good or even great FPGA developer. Since I get asked quite often, I decided to put my thoughts down here instead of typing it out again and again forever. I hope what I write here will help you on your journey. I think some of the content might be useful to non-FPGA developers even though I don’t really plan for it to be as such.
This article is meant for readers who have already made it through their first FPGA course, maybe they are in a masters program or they might be in the first few years of their new job as an FPGA developer. It is not really meant for beginners but might be useful for them none the less.
Continue reading Growing as an FPGA Developer
One of the most annoying things when working on an early design on an FPGA development kit is a lack of run-time register interfaces without a lot of effort.
While looking for an interface that would work on basically any Vivado supported Xilinx FPGA I came across the JTAG to AXI Master core supplied by Xilinx. Unfortunately it has a cumbersome interface that is intended for the user to drive from Vivado’s TCL console which is not always the most convenient. Others have been looking for a C API to interact with the hw_server directly. There seems to be someone that has had put together a C library but I was unable to get the files. I wanted something easier to use anyways so I began to look elsewhere for a solution.
Continue reading FPGA – Xilinx JTAG to AXI Master from XSDB and Python
LittleRiscy is an RV32I RISC-V emulator and HDL core that I have decided to release as an open source project. The project is a work in progress.
LittleRiscy’s GIT repository contains an instruction set emulator written in C++ and a CPU core written in SystemVerilog. The emulator has been validated against some simple test binaries and the SystemVerilog code has been converted to C++ using Verilator to validate that it behaves functionally identical when running the same test binaries.
At this time, LittleRiscy has been deployed on a Xilinx Series 7 FPGA using Xilinx Vivado and has blinked some LEDs with a simple binary.
The goal of LittleRiscy is to create a simple CPU core for a unique purpose. It will be a classic RISC pipeline with no debugger, no interrupts, no ability to load new code at runtime, and limited peripherals. Inspired by CHIPS2.0 and the PIOs in the RP2040, it will be used to process AXI-Streams for packet processing or digital signal processing when data rates are low enough that custom RTL logic is not required and a CPU is both smaller and simpler. To further simplify creation of software for the core, the AXI-Stream input interface could stall the CPU on read if empty and the output interface could stall the CPU on write if full, negating the requirement for the software to check flags during execution. For some demanding tasks, it should be easy to add a handful of custom instructions to improve throughput.
Recently I started using an FTDI FT232H in FT245 synchronous FIFO mode with an Intel MAX10 FPGA. I am using an FT232R based USB Blaster (Not a USB Blaster II, this is an older Altera USB Blaster, Terasic USB Blaster or another clone). Unfortunately when Quartus looks for programming devices it fails if it sees the FT232H first and the FT232H is in use by another program.
Continue reading FPGA – Conflicting FTDI Devices in Quartus